Di Geng

 TFTs for Display


Key Laboratory of Microelectronics Devices and Integrated Technology, Institute of Microelectronics of the Chinese Academy of Sciences, Beijing, China



Email: digeng@ime.ac.cn





Di Geng received Ph.D. degree in information display from the Kyung Hee University, Seoul,Korea, where he is currently an associate professor with the institute of Microelectonics of Chinese Academy of Science, Beijing, China.

He was involved in several display and sensor technology development with BOE and Huawei, and leading the new structure oxide TFT development with Hisilicon.

His current research interests include fabrication and design of high performance Oxide TFT and circuits for flexible display application and beyond.

Abstract for Presentation

High Performance Sub-50nm Channel Length Vertical IGZO TFTs for Active Matrix Application



Oxide semiconductor-based Thin-Film-Transistors (TFTs) such as IGZO-TFTs have been widely investigated in the past double decades due to the advantages of high mobility (>10 cm2/Vs), good uniformity and low process temperature (<400℃) [1-2]. These features enable the application of IGZO TFTs in high performance display panels, such as active-matrix organic light emitting diode (AMOLED). With the development of virtual reality, the high-resolution displays have attracted considerable attention. For the high-resolution display, the pixel area should be reduced by scaling down the channel length to sub-micron region or developing new structure. From the transistor point of view, vertical-channel structure enables a higher density owing to its smaller footprint compared to the planar structure [3-4].

In this work, we propose a novel vertical channel-all-around structure where the gate electrode is surrounded by a gate insulator and an IGZO channel, and its source/drain electrodes are vertically separated by an insulator layer, forming a metal/insulator/metal (MIM) structure. The channel and gate stack is deposited by Plasma-Enhanced Atomic Layer Deposition (PEALD). The impacts of IGZO cycle ratio and plasma power on the device electrical performance are studied. An optimized 50nm-channel-length vertical IGZO FET achieved Ion >30µA/µm and Ioff below 1.8×10-17µA/µm at VDS = 1V.






[1] T. Kamiya, et al., “Material characteristics and applications of transparent amorphous oxide semiconductors,” NPG Asia Mater. 2(1) pp. 15-22 (2010).

[2] Nomura, K., et al. "Room-temperature fabrication of transparent flexible thin-film transistors using amorphous oxide semiconductors. " Nature 432.7016(2004):488-492.

[3] Jong-Beom, et al. "Oxide Vertical TFTs for the Application to the Ultra High Resolution Display." SID International Symposium: Digest of Technology Papers 47.2(2016):820-822.

[4] Yeo-Myeong, et al. "Improvement in Device Performance of Vertical Thin-Film Transistors Using Atomic Layer Deposited IGZO Channel and Polyimide Spacer." IEEE Electron Device Letters 38.10(2017):1387-1389.